1. Field of the Invention
The present invention relates to a nonvolatile memory, and more particularly, to a nonvolatile memory and a method for fabricating the same, which can prevent damage to a diffusion region between a selection transistor and a memory cell transistor and reduce cell size.
2. Background of Related Art
An MOS (Metal On Insulator) memory (which holds information recorded in a cell even after power is cut off) is a nonvolatile memory that has applications in fields of power-on program storage media (for example, built in a computer bios program, various equipment set-up program and the like), operation program memories for vending machine/ticketing machine, font storage media for computer/printer and etc., game machine and the like. In general, nonvolatile memories include MASK ROM, PROM, EPROM, EEPROM and flash EEPROM. An EEPROM (Electrically Erasable and Programmable Read Only Memory) will be explained as an example with respect to the related art and to the present invention.
A related art nonvolatile memory will be explained with reference to the attached drawings. FIG. 1 illustrates a layout of the related art nonvolatile memory. FIG. 2 illustrates a section across line Ixe2x80x94I in FIG. 1. FIG. 3 illustrates a section across line IIxe2x80x94II in FIG. 1. FIG. 4 illustrates a section across line IIIxe2x80x94III in FIG. 1.
Referring to FIGS. 1xcx9c4, a related art EEPROM cell is provided with a semiconductor substrate 10 having an active region and a field region. The active region has a selection transistor region xe2x80x98Axe2x80x99 and a cell transistor region xe2x80x98Bxe2x80x99 defined therein. First and second gate oxide films 12a and 12b are formed in different thicknesses on the selection transistor region xe2x80x98Axe2x80x99 and the cell transistor region xe2x80x98Bxe2x80x99 on the semiconductor substrate 10, respectively. A selection gate line 13a is formed on a region of the second gate oxide film 12a in the selection transistor region xe2x80x98Axe2x80x99 in one direction. A floating gate pattern 13b and an insulating film 14 are formed on a region of the second gate oxide film 12b in the cell transistor region xe2x80x98Bxe2x80x99 in a direction identical to the direction of the selection gate line 13a at a fixed interval. A control gate 15a is formed on the insulating film 14 in a direction identical to the direction of the floating gate pattern 13b. Impurity diffusion regions 17 of a conductivity type opposite to that of the semiconductor substrate 10 are formed in the semiconductor substrate 10 on both sides of the selection gate line 13a and the floating gate pattern 13b/the control gate line 15a. The impurity diffusion regions 17 are impurity regions used as source and drain regions. A bit line 20 is formed to cross the selection gate line 13a and the control gate line 15a. The unexplained reference numerals 18 and 21 are first and second interlayer insulating films, 19 is a bit line contact hole, 22 is a selection gate contact region and 23 is a common source contact region.
A related art method for fabricating the aforementioned nonvolatile memory will be explained with reference to the attached drawings. FIGS. 5axcx9c5g illustrate sections across line IVxe2x80x94IV in FIG. 1 for showing the steps of a related art method for fabricating a nonvolatile memory.
Referring to FIG. 5a, the related art method for fabricating a nonvolatile memory starts with forming a field insulating film 11 on a field region of a semiconductor substrate 10 having a selection transistor region xe2x80x98Axe2x80x99, a cell transistor region xe2x80x98Bxe2x80x99 and the field region defined thereon. Then, a first and a second gate oxide films 12a and 12b with thicknesses different from each other are formed on the selection transistor region xe2x80x98Axe2x80x99 and the cell transistor region xe2x80x98Bxe2x80x99; respectively. The first gate oxide film 12a on the selection transistor region xe2x80x98Axe2x80x99 is thicker than the second gate oxide film 12b on the cell transistor region xe2x80x98Bxe2x80x99. The thin second gate oxide film 12b on the cell transistor region xe2x80x98Bxe2x80x99 is a tunneling oxide film. As shown in FIG. 5b, a first polysilicon layer is deposited on an entire surface, and the first polysilicon layer on regions of the first and second gate oxide films 12a and 12b are selectively patterned (photolithography+etching), to form a selection gate line 13a on the selection transistor region xe2x80x98Axe2x80x99 and a floating gate pattern 13b on the cell transistor region xe2x80x98Bxe2x80x99. Then, an insulating film 14 is formed on entire surfaces of the first and second gate oxide films 12a and 12b including the selection gate line 13a and the floating gate pattern 13b. The insulating film 14 has an ONO (Oxide Nitride Oxide) structure. Though not shown in the FIGS. 5a-5g, the floating gate pattern 13b, patterned in a horizontal direction, is separated in rectangular portions. As shown in FIG. 5c, a second polysilicon layer 15 is formed on an entire surface of the insulating film 14. As shown in FIG. 5d, a first photoresist film PRI is coated on the second polysilicon layer 15 and subjected to selective patterning by exposure and development, to remove the first photoresist film PR1 from upper portions of the selection transistor region xe2x80x98Axe2x80x99 and from a part of the cell transistor region xe2x80x98Bxe2x80x99 adjacent to the selection transistor region xe2x80x98Axe2x80x99. The patterned first photoresist film PR1 is used as a mask to remove the second polysilicon layer 15 selectively, to leave the second polysilicon layer 15 only on the insulating film 14 on the cell transistor region xe2x80x98Bxe2x80x99. If the second polysilicon layer 15 is left only on a region on which the control gate line is to be formed for forming the control gate line (because the selection gate line 13a is also etched as the floating gate pattern 13b under the control gate line is etched), only the second polysilicon layer 15 on the selection transistor region xe2x80x98Axe2x80x99 is removed at first. Then, as shown in FIG. 5e, the first photoresist film PR1 is removed, and a second photoresist film PR2 is coated on the second polysilicon layer 15 including the insulating film 14, and subjected to patterning by exposure and development, to leave one portion of the second photoresist film PR2 on an entire surface of the selection transistor region xe2x80x98Axe2x80x99 and the other portion on the second polysilicon layer 15 over the floating gate pattern 13b on the cell transistor region xe2x80x98Bxe2x80x99 spaced from the one portion over the selection transistor region xe2x80x98Axe2x80x99. The patterned second photoresist film PR2 is used as a mask in selectively etching and removing the second polysilicon layer 15 and portions of the floating gate pattern 13b, to form a control gate line 15a. Upon etching the second polysilicon layer 15 and the floating gate pattern 13b of the first polysilicon layer, the part of semiconductor substrate 10 not masked by the second photoresist film PR2 at an interface of the selection transistor region xe2x80x98Axe2x80x99 and the cell transistor region xe2x80x98Bxe2x80x99 is also etched to form a trench 16, because of different etch selectivities and etch rates. In general, though an oxide film, a nitride film and a polysilicon layer differ in their respective etch selectivities, the etching time period must be watched carefully because an oxide film and a nitride film are etched to some extents when a polysilicon layer is etched. Under the same etch conditions, an etch rate of the nitride film is higher than the etch rate of the polysilicon layer, and an etch rate of the oxide film is higher than the etch rate of the nitride film. Because of these reasons, when the second polysilicon layer 15 and the floating gate pattern 13b are etched, the ONO-structured insulating film 14, the thin second gate oxide film 12b, and the semiconductor substrate 10 are also etched, forming the unnecessary trench 16. As shown in FIG. 5f, the second photoresist film PR2 is removed, and the selection gate line 13a and the control gate line 15a are used as a mask in conducting an ion injection to form impurity regions 17 in the semiconductor substrate 10 on both sides of the selection gate line 13a and the control gate line 15a. A first interlayer insulating film 18 is deposited on an entire surface of the semiconductor substrate 10 including the selection gate line 13a and the control gate line 15a. A bit line contact region is defined therein, and the first interlayer insulating film 18, the insulating film 14 and the first gate oxide film 12a, all of which are in the bit line contact region, are subjected to selective patterning (photolithography+etching), to form a bit line contact hole 19. Then, a bit line 20 is formed on an entire surface of the first interlayer insulating film 18 including the bit line contact hole 19 and subjected to patterning to a fixed width. As shown in FIG. 5g, a second interlayer insulating film 21 is deposited on the first interlayer insulating film 18 including the bit line 20. In addition to this, a signal application region for the selection gate line 13a is defined at one side of the bit line 20(see FIG. 1), and the first and second interlayer insulating films 18 and 21 over the selection gate line 13a are selectively removed to form a selection gate contact hole 22. And, a common source contact region 23 is formed in an N+ diffusion region in the cell transistor region xe2x80x98Bxe2x80x99.
However, the related art nonvolatile memory and method for fabricating the same have the following problems.
The formation of unneccesary trench in the semiconductor substrate between the selection transitor region and the cell transistor region leads irregularly-shaped impurity regions, which reduces device reliability.
Accordingly, the present invention is directed to a nonvolatile memory and a method for fabricating the same that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a nonvolatile memory and a method for fabricating the same which can prevent damage to impurity regions between a selection transistor and a cell transistor and reduce resistance of the selection transistor.
Another object of the present invention is to provide a nonvolatile memory and a method for fabricating the same which can reduce a space between the selection transistor and the cell transistor to reduce cell size.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the nonvolatile memory includes a semiconductor substrate having a selection transistor and a cell transistor defined thereon, a first selection gate line formed on the selection transistor region in one direction and a floating gate formed on the cell transistor region in a fixed pattern, an insulating film and a second gate line formed on the first selection gate line at fixed intervals, and an insulating film and a control gate line over the insulating film including the floating gates in the same direction as the first gate line, impurity regions formed in one region in the semiconductor substrate on both sides of the control gate line and the first selection gate line, a first planar protection film having first contact holes one each exposing the first selection gate line and the impurity region, respectively, a contact plug in the first contact hole, a conductive layer pattern in contact with the contact plug, a second planar protection film having a contact hole to the conductive layer pattern over the first selection gate line, and a wiring line formed on the second contact hole and the second planar protection film in one direction.
In another aspect of the present invention, there is provided a method for fabricating a nonvolatile memory, comprising the steps of (1) forming a gate insulating film on a semiconductor substrate having a selection transistor region and a cell transistor region defined thereon, (2) patterning the first semiconductor layer in line forms in the selection transistor region and to be spaced from one another at fixed intervals in the cell transistor region, (3) depositing an insulating film and a second semiconductor layer on an entire surface of the semiconductor substrate, (4) subjecting the first and second semiconductor layers and the insulating film to etching, so that a line form of a first selection gate line disposed in one direction and a second selection gate line isolated for a distance disposed on the first selection gate line are formed on the selection transistor region, and so that floating gates patterned into fixed forms and a line form of control gate line disposed on the insulating film including the floating gates are formed in one direction, (5) forming impurity regions in one region in the semiconductor substrate on both sides of the first selection gate line and the control gate line, (6) forming a first planar protection film having first contact holes one each to the first selection gate line and to the impurity region on one side of the gate line, (7) forming a contact plug in each of the first contact holes, (8) forming a conductive layer pattern on the contact plugs and the first planar protection film, (9) forming a second planar protection film having a second contact hole to the contact plug on the first selection gate line, and (10) forming a conductive line in one direction both on the second contact hole and the second planar protection film.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.